Verilog engineer job offers
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(Sr. /Staff) NPU Design Engineer
OMNIVISION Singapore, Singapore
...Being part of modelling the performance of the NPU module and its data transaction throughput. Microarchitecture design and RTL coding using Verilog...
25 days ago in JobleadsReport -
Memory Design Automation – Memory modeling Engineer
PERSOL SINGAPORE PTE. Singapore, Singapore
...verilog. Knowledge and experience with EDA simulation tools such as VCS, NC is required. Experience with EDA tools will be helpful: DFT: Logicvision...
26 days ago in JobrapidoReport -
(Sr. /Staff) SoC Design Engineer
OmniVision Technologies Singapore, Singapore
About the job (Sr. /Staff) SoC Design Engineer Description You would be part of a dynamic digital SoC design team that develops state‑of‑the‑art video...
25 days ago in JobleadsReport -
(Sr. /Staff) IP Design Engineer
OVT group Singapore, Singapore
...accelerators, etc. Responsibilities Develop design requirements from a given system level specifications. Microarchitecture design and RTL coding using Verilog...
30+ days ago in JobleadsReport -
(Sr. /Staff) IP Design Engineer
OMNIVISION Singapore, Singapore
...accelerators, etc. Responsibilities Develop design requirements from given system level specifications. Microarchitecture design and RTL coding using Verilog...
30+ days ago in JobleadsReport -
Senior Staff Engineer, Analog IC Design
Confidential Singapore, Singapore
...Verilog, etc. Lab testing skills to evaluate the prototype unit to the design specification. Job Responsibilities Work with multi-functional teams to...
30+ days ago in MonsterReport -
(Sr. /Staff) IP Design Engineer
OMNIVISION Singapore, Singapore
...accelerators, etc. Responsibilities Develop design requirements from a given system level specifications. Microarchitecture design and RTL coding using Verilog...
25 days ago in JobleadsReport -
Sr/ IC Design Engineer (Design Verification)
ETHOS SEARCH ASSOCIATES PTE. Singapore, Singapore
...(Verilog, VHDL) Experience in using leading EDA software tools like Cadence/ Synopsys Ethos Search Associates Pte. Ltd. EA Licence No: 13C6655 EA Reg No...
30+ days ago in JobrapidoReport -
Sr/ IC Design Engineer (Design Verification)
ETHOS TECH ONE PTE. Singapore, Singapore
...communication and Analytical skills Understanding of HDL (Verilog, VHDL) Experience in using leading EDA software tools like Cadence/ Synopsys #J-18808-Ljbffr
30+ days ago in JobrapidoReport -
Principal DFT Engineer (Design-For-Test)
VOICE THE WAY PTE. Singapore, Singapore
...Verilog and familiarity with front-end design flow; Knowledge of DFT concepts and techniques, including scan insertion, MBIST, and boundary scan; Proficient...
19 days ago in JobrapidoReport -
Digital Frontend Design Engineer（SG）
Canaan Singapore, Singapore
...ownership of the full project lifecycle, from architecture to production. 5+ years of experience in ASIC frontend design. Strong proficiency in Verilog/VHDL...
30+ days ago in JobleadsReport -
Standard Cell Library Design Engineer
Confidential D27, Singapore, Singapore
...verilog, lef, liberty and other industry standard EDA models Familiarity with EDA tools used in STA and PnR Experience with. Lib syntax including...
14 days ago in MonsterReport -
Standard Cell Library Design Engineer
Confidential D27, Singapore, Singapore
...verilog, lef, liberty and other industry standard EDA models Familiarity with EDA tools used in FE (Extraction, sims, char) and BE (Verification, STA, P&R...
14 days ago in FounditReport -
Standard Cell Library Design Engineer
Broadcom Singapore, Singapore
...circuit design knowledge Understanding of cell layout or physical design Understanding of FinFet, RibbonFet/GAA process nodes Understanding of verilog...
15 days ago in JobrapidoReport -
ASIC/SoC Design Verification Engineer SG
TetraMem - Accelerate The World Singapore, Singapore
ASIC/SoC Design Verification Engineer SG – TetraMem. Accelerate The World Join to apply for the ASIC/SoC Design Verification Engineer SG role at TetraMem...
10 days ago in JobleadsReport -
Pre-Silicon Chip Verification Engineer (UVM/SystemVerilog)
CANAAN CREATIVE GLOBAL PTE. Singapore, Singapore
A technology development company in Singapore is seeking a skilled engineer to perform chip verification for new product development. The ideal candidate...
9 days ago in JobleadsReport -
Senior NPU Design Engineer - Low-Power SoC Architect
OMNIVISION Singapore, Singapore
A leading semiconductor manufacturer in Singapore is seeking an experienced design engineer to focus on NPU development. This role involves developing design...
25 days ago in JobleadsReport -
Senior Staff Engineer, Physical Design
Confidential Singapore, Singapore
...such as Perl, tcl, and Python Good object-oriented programming skills Good understanding of digital logic and computer architecture Knowledge of Verilog/VHDL...
27 days ago in MonsterReport -
Synthesis & STA Engineer - Singapore
ByteDance Singapore, Singapore
...Verilog/SystemVerilog, RTL‑to‑GDSII flow, and EDA tools (Fusion Compiler, Genus/Innovus+, PrimeTime/Tempus, Formality, Conformal LP). Preferred...
19 days ago in JobrapidoReport -
Synthesis & STA Engineer - Singapore
Confidential Singapore, Singapore
...Verilog/SystemVerilog, RTL-to-GDSII flow, and EDA tools (Fusion Compiler, Genus/Innovus+, PrimeTime/Tempus, Formality, Conformal LP). Preferred...
23 days ago in MonsterReport -
Senior Firmware Engineer (FPGA)
AES GLOBAL HOLDINGS PTE. Serangoon Garden Circus, Southeast
...Verilog or VHDL. FPGA measurements and control of devices in VHDL. SPI bus or similar interface knowledge required. Knowledge of revision control, vaults...
11 days ago in JobleadsReport -
Staff Silicon Design Engineer – RTL
AMD Singapore, Singapore
Join to apply for the Staff Silicon Design Engineer – RTL role at AMD. Get AI-powered advice on this job and more exclusive features. WHAT YOU DO AT AMD...
25 days ago in JobleadsReport -
Principal Analog Mixed-Signal Design Engineer
Astera Labs D19, Singapore, Singapore
Principal Analog Mixed-Signal Design Engineer Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and...
30+ days ago in JobleadsReport -
Standard Cell Library Design Engineer
Broadcom Singapore, Singapore
Standard Cell Library Design Engineer page is loaded# Standard Cell Library Design Engineerlocations: Singapore-Yishuntime type: Full timeposted on: Posted...
13 days ago in JobleadsReport -
Standard Cell Library Design Engineer
Broadcom Singapore, Singapore
Standard Cell Library Design Engineer page is loaded# Standard Cell Library Design Engineerlocations: Singapore-Yishuntime type: Full timeposted on: Posted...
15 days ago in JobrapidoReport
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