Verilog engineer job offers
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Staff Front-End Engineer
BITDEER DEVELOPMENT PTE. Singapore, Singapore
...Headquartered in Singapore, Bitdeer has deployed datacenters in the United States, Norway, and Bhutan. What you will be responsible for Implement Verilog...
4 days ago in JobleadsReport -
IP Design Engineer
new Best NanoTech D1, Singapore, Singapore
...accelerators, etc. ResponsibilitiesDevelop design requirements from a given system level specifications. Microarchitecture design and RTL coding using Verilog...
1 day ago in WhatjobsReport -
Senior Design Verification Engineer
new jondavidson D1, Singapore, Singapore
...Verilog Assertions (SVA) C/C+ languageFormal Methodology (e. G JasperGOLD) Coverage analysisLow-power verification. Scripting languages (e.g perl, tcl...
1 day ago in WhatjobsReport -
Digital Circuit Verification Engineer
new BITMAIN D1, Singapore, Singapore
...Verilog or SystemVerilog syntax, and skilled in using scripting languages such as C/Tcl/Shell/Perl/Python; 3. Familiar with SDC constraint writing rules...
1 day ago in WhatjobsReport -
(Sr. /Staff) NPU Design Engineer
OmniVision Technologies Singapore, Singapore
...Being part of modelling the performance of the NPU module and its data transaction throughput. Microarchitecture design and RTL coding using Verilog...
2 days ago in FounditReport -
ASIC Design Engineer
new Black Sesame Technologies (Singapore) D1, Singapore, Singapore
...the design meets rigorous timing and power requirements. Responsibilities: RTL Design: Implement high-efficiency logic modules using SystemVerilog/Verilog...
1 day ago in WhatjobsReport -
Principal Front End Engineer
BITDEER DEVELOPMENT PTE. Singapore, Singapore
...Headquartered in Singapore, Bitdeer has deployed datacenters in the United States, Norway, and Bhutan. What you will be responsible for Implement Verilog...
4 days ago in JobleadsReport -
ASIC Design Engineer
new Black Sesame Singapore, Singapore
...the design meets rigorous timing and power requirements. Responsibilities RTL Design: Implement high-efficiency logic modules using SystemVerilog/Verilog...
18 h 40 minutes ago in WhatjobsReport -
Senior Firmware Engineer
new Advanced Energy Management Singapore, Singapore
...Verilog or VHDL. FPGA measurements and control of devices in VHDL. SPI bus or similar interface knowledge required. Knowledge of revision control, vaults...
11 h 2 minutes ago in WhatjobsReport -
Design Verification Engineer
new UNI CONNECT Singapore, Singapore
Design Verification Engineer We are looking for an experienced Design Verification Engineer. The ideal candidate will have 4-8 years of experience in the...
1 day ago in WhatjobsReport -
(Sr. /Staff) SoC Design Engineer
OMNIVISION Singapore, Singapore
...to meet or exceed the technical requirements of the SoC. You would be responsible for the successful implementation of the designs in Verilog/SystemVerilog...
4 days ago in FounditReport -
Senior Firmware Engineer
new Advanced Energy D1, Singapore, Singapore
...Verilog or VHDL. FPGA measurements and control of devices in VHDL. SPI bus or similar interface knowledge required. Knowledge of revision control, vaults...
1 day ago in WhatjobsReport -
MTS Silicon Design Engineer
AMD Singapore, Singapore
...Verilog, C, and C+ Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a...
6 days ago in JobleadsReport -
MTS Silicon Design Engineer
new AMD D1, Singapore, Singapore
...Verilog, C, and C+ Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a...
1 day ago in WhatjobsReport -
Semiconductor Design Verification Engineer
new Realtek Singapore Private D4, Singapore, Singapore
...Verilog/ UVM experience. Familiar with ASIC verification methodology, tools, and development flow. Working experience or familiar with Ethernet L2/L3...
1 day ago in WhatjobsReport -
Senior Staff Engineer - RTL
Ambiq Micro Singapore, Singapore
...Verilog. 3rd party IP identification, selection, and integration. Collaboration with verification and FPGA teams in test plan development and debug...
3 days ago in WhatjobsReport -
Standard Cell Library Design Engineer
Broadcom D27, Singapore, Singapore
...verilog, lef, liberty and other industry standard EDA models Familiarity with EDA tools used in FE (Extraction, sims, char) and BE (Verification, STA, P&R...
4 days ago in FounditReport -
Senior Library Characterization Engineer
Bitdeer (NASDAQ: BTDR) Singapore, Singapore
Senior Library Characterization Engineer 4 days ago Be among the first 25 applicants About Bitdeer Bitdeer Technologies Group (Nasdaq: BTDR) is a...
3 days ago in WhatjobsReport -
Staff ME Engineer
BITDEER DEVELOPMENT PTE. Singapore, Singapore
...Verilog/SystemVerilog, RTL-to-GDSII flow, and EDA tools (Synopsys Design Compiler, Cadence Genus, PrimeTime, Innovus). Strong understanding of timing...
5 days ago in JobleadsReport -
Senior Library Characterization Engineer
Bitdeer Group Singapore, Singapore
Senior Library Characterization Engineer Bitdeer Technologies Group (Nasdaq: BTDR) is a world-leading technology company for Bitcoin mining. Bitdeer is...
3 days ago in WhatjobsReport -
Senior Front-End Engineer
new Bitdeer (NASDAQ: BTDR) D1, Singapore, Singapore
...Headquartered in Singapore, Bitdeer has deployed datacenters in the United States, Norway, and Bhutan. What You Will Be Responsible ForImplement Verilog...
1 day ago in WhatjobsReport -
Senior Hardware Engineer
new Rapsodo D1, Singapore, Singapore
...Experience in logic design for FPGA using VHDL/Verilog is a plus Ability to work in a dynamic environment with good communication and interpersonal skills
1 day ago in WhatjobsReport -
Research Engineer (Battery Monitoring Hardware)
National University of Singapore Singapore, Singapore
...skills for high-performance MCUs. Proficiency in Verilog for high-speed signal processing and complex timing generation. Open to Fixed Term Contract.
2 days ago in FounditReport -
Principal Mid-End Engineer
BITDEER DEVELOPMENT PTE. Singapore, Singapore
...Verilog/SystemVerilog, RTL-to-GDSII flow, and EDA tools (Synopsys Design Compiler, Cadence Genus, PrimeTime, Innovus). Strong understanding of timing...
4 days ago in JobleadsReport -
Lead engineer-Design verification
new Uni Connect Singapore, Singapore
...Verilog, C/C+, Python, Perl or Makefile Technologies: ARM M/RISC-V (Preferred), AMBA AXI/AHB/APS, DMA, Flow Control, Serial Devices, Qo5 Preferred...
1 day ago in JobleadsReport
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