Verilog engineer job offers
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FPGA Engineer
KEYSIGHT TECHNOLOGIES SINGAPORE (SALES) PTE. Singapore, Singapore
...Verilog, and other hardware description languages. Experience with simulation tools and FPGA development environments. Strong problem-solving abilities...
29 days ago in JobrapidoReport -
Senior Staff/ Design Verification Engineer
Silicon Labs D1, Singapore, Singapore
...Verilog A, C, and TCLKnowledge of industry-standard interfaces. Tools proficiency in Xcelium, Spectre, Questasim, SymphonyScripting skills in languages like...
6 days ago in WhatjobsReport -
Senior / Engineer, Digital IC Design (Semiconductor)
jondavidson D1, Singapore, Singapore
...Verilog or VHDL). Good experience in cdc, rdc, lint. Some exposure to Scripting languages (PERL, TCL, PYTHON). Ability to interface with cross-functional...
6 days ago in WhatjobsReport -
Staff Digital IC Design Engineer
Zerro Power Systems Singapore, Singapore
...Engineering with Mixed Signal IC design/verification experience. At least 7-10 Year(s) of working experience in application/validation Fluent in Verilog...
7 days ago in JobleadsReport -
Senior Engineer, Digital IC Design
jondavidson D1, Singapore, Singapore
...Verilog or VHDL). Good experience in cdc, rdc, lint. Some exposure to Scripting languages (PERL, TCL, PYTHON). Ability to interface with cross-functional...
6 days ago in WhatjobsReport -
ASIC/SoC Design Verification Engineer SG
Tetramem D1, Singapore, Singapore
...Verilog, Python/Perl/TCL/Shell scripting, C/C+, System C and industry mainstream ISAs assembly codingFamiliarity with MIPI, AMBA (APB/AHB/AXI) bus protocol...
6 days ago in WhatjobsReport -
FPGA Engineer
Confidential D27, Singapore, Singapore
...Verilog, and other hardware description languages. Experience with simulation tools and FPGA development environments. Strong problem-solving abilities...
30+ days ago in FounditReport -
Senior Principal SOC Design Engineer
MaxLinear D1, Singapore, Singapore
ResponsibilitiesMaxLinear is seeking a Senior Principal SOC Design Engineer to join our VLSI group. You will be responsible for pre-silicon RTL coding of...
6 days ago in WhatjobsReport -
ASIC/SoC Design Verification Engineer SG
new Tetramem Singapore, Singapore
...Verilog, Python/Perl/TCL/Shell scripting, C/C+, System C and industry mainstream ISAs assembly coding Familiarity with MIPI, AMBA (APB/AHB/AXI) bus protocol...
6 h 16 minutes ago in JobleadsReport -
ASIC Design Verification Engineer
TetraMem
...Verilog, Python/Perl/TCL/Shell scripting, C/C+, System C and industry mainstream ISAs assembly codingFamiliarity with MIPI, AMBA (APB/AHB/AXI) bus protocol...
6 days ago in WhatjobsReport -
Senior Design Verification Engineer
Uni Connect
...Requirements. Bacheloror Master degree, majoring Electrical or Computer Engineering; 3~5years working experiences as either Designer or Verification Engineer...
6 days ago in WhatjobsReport -
Senior Silicon Design Engineer (FPGA)
xilinx asia pacific Singapore, Singapore
...Verilog Strong debug skills Scripting experience using Perl, Python, TCL, C-shell, Make and/or other scripting languages Knowledge and experience with basic...
3 days ago in JobleadsReport -
FPGA Engineer
Keysight Technologies Singapore, Singapore
...Verilog, and other hardware description languages. Experience with simulation tools and FPGA development environments. Strong problem‑solving abilities...
30+ days ago in JobrapidoReport -
Semiconductor Senior Design Verification Engineer
Realtek Singapore Private D4, Singapore, Singapore
...Verilog, UVM, Python (TCL/Perl a plus) Familiar with ASIC verification methodology, tools, and development flow. Preferred Working experience: Ethernet...
6 days ago in WhatjobsReport -
Standard Cell Library Design Engineer
Broadcom D3, Singapore, Singapore
...circuit design knowledge. Understanding of cell layout or physical design. Understanding of FinFet, RibbonFet/GAA process nodes. Understanding of verilog...
6 days ago in WhatjobsReport -
ASIC RTL/SoC Design Engineer SG
Tetramem D1, Singapore, Singapore
...Verilog and SystemVerilogExperience with VCS, Verdi or other industry standard toolsExperience with pre-layout simulation and post-layout...
6 days ago in WhatjobsReport -
ASIC RTL Design Engineer
TetraMem
...junior engineers QualificationsMS with 5+ years of experience or PhD in Electrical Engineering with emphasis on RTL/SoC/digital designExperience with Verilog...
6 days ago in WhatjobsReport -
Snr Staff Physical Design Engineer
ADVANCED MICRO DEVICES (SINGAPORE) Singapore, Singapore
...PERSON: Strong communication skills, ability to multi-task across projects, and work with geographically spread-out teams KEY RESPONSIBILITIES: This Engineer...
3 days ago in JobleadsReport -
Design Verification Engineer
Confidential Singapore, Singapore
Design Verification Engineer Experience: 4+ Years Skills Required: FPGA SoC Verification Skills ASIC SoC Verification Skills System Verilog and UVM Skills...
21 days ago in MonsterReport -
ASIC RTL/SoC Design Engineer SG
new Tetramem Singapore, Singapore
...Verilog and SystemVerilog Experience with VCS, Verdi or other industry standard tools Experience with pre-layout simulation and post-layout simulation...
6 h 20 minutes ago in JobleadsReport -
Senior Staff Engineer, Analog IC Design
Marvell Technology D1, Singapore, Singapore
...Verilog, etc. Lab testing skills to evaluate the prototype unit to the design specification. Additional Compensation and Benefit ElementsWith competitive...
6 days ago in WhatjobsReport -
Senior Staff Engineer, Physical Design
Marvell Technology D1, Singapore, Singapore
...Verilog. Good communication skills and self-discipline contributing in a team environment. Experience with multi-voltage and low-power design techniques is...
6 days ago in WhatjobsReport -
Senior Staff Engineer, Analog IC Design
Marvell Technology D1, Singapore, Singapore
...Verilog, etcA thorough understanding of the physical layout requirements and ability to perform the critical layouts for analog circuits. Lab testing skills...
6 days ago in WhatjobsReport -
Research Associate/Engineer II
Nanyang Technological University
...Verilog or VHDLStrong understanding of digital design principles and embedded systemsProficiency in low-level programming languages such as C, Rust and...
2 days ago in WhatjobsReport -
Design Engineer (ASIC)
Confidential Singapore, Singapore
Responsibilities: Assist in designing micro-architecture for ISP and CV algorithms. Perform RTL design using Verilog/System Verilog and HLS tools (Catapult)...
19 days ago in MonsterReport
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