Verilog engineer job offers
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FPGA Engineer
new Citadel Securities Singapore, Singapore
...Verilog or VHDL (Python, C, Tcl, and bash a plus) Experience in one or more of the following areas: Hardware Architecture, RTL Coding, Simulation, Systems...
1 day ago in Talent.comReport -
Staff NPU Design Engineer
new EnviroDynamics Solutions Singapore, Singapore
...on system-level requirements. Develop performance models to evaluate design trade-offs. Design and implement NPU microarchitecture using Verilog/SystemVerilog...
1 day ago in Talent.comReport -
Senior/Manager DFT Engineer
new Helius Singapore, Singapore
Senior Role: We are seeking a skilled Senior Engineer to join our team and contribute to the design and development of our advanced semiconductor products...
1 day ago in Talent.comReport -
(Staff/Sr. Staff) NPU Design Engineer
OMNIVISION Singapore, Singapore
...Being part of modelling the performance of the NPU module and its data transaction throughput. Microarchitecture design and RTL coding using Verilog...
5 days ago in Talent.comReport -
Application Engineer (FPGA/Analog/MCU/Verilog)
new STAFFKING PTE. Singapore, Singapore
...technical support for customer projects involving FPGA (e... Intel, Lattice), analog circuits, microcontrollers (MCUs), and digital designs using Verilog...
1 day ago in WhatjobsReport -
ISP RTL Design Engineer
OmniVision Technologies Singapore, Singapore
Responsibilities Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis) Verify Logic at ISP...
6 days ago in JobrapidoReport -
Engineer / Senior Engineer – IC Verification
new Helius Singapore, Singapore
...Verilog and UVM verification methodology. Experience in using EDA tools from Cadence, Synopsys. Knowledge and working experience in one or more of the...
1 day ago in Talent.comReport -
ISP RTL Design Engineer
OMNIVISION
Description Responsibilities Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis) Verify...
4 days ago in Talent.comReport -
Field Application Engineer - FPGA
Adecco
...provider in RF and Microwave technologies, and value-added manufacturing for the electronics industry. We are searching for a FPGA Field Application Engineer...
3 days ago in Talent.comReport -
FPGA Design Engineer
KLA
Description /Preferred Qualifications KLA is seeking a talented and motivated senior engineer to fill new position within the Pro engineering group. Our...
3 days ago in Talent.comReport -
IC Design Engineer (Verilog, EDA, up to $10,000)
RECRUIT EXPERT PTE. Singapore, Singapore
...Verilog HDL and VHDL RTL design, Logic Synthesis, DFT, ATPG, Timing ClosureIf you are keen to apply for the position, kindly email your detailed resume inMS...
2 days ago in WhatjobsReport -
Digital IC Verification Engineer
Confidential Singapore, Singapore
...Verilog and proficient in C / SystemVerilog for verification Proficient in scripting languages such as Perl / Shell / Tcl Familiarity with VMM / UVM is a...
4 days ago in FounditReport -
Senior/Principal Engineer, Probe
new Micron
...Support for New Product Design Verification: The role provides support for design verification and in-depth circuit of new products using CAD tools and Verilog...
1 day ago in Talent.comReport -
Senior Software Development Engineer II
new Silicon Labs
...and cutting-edge algorithms, all meticulously tuned to deliver perfection at microscopic scales. We are looking for a talented and driven software engineer...
1 day ago in Talent.comReport -
Senior Staff/ Design Verification Engineer
new Silicon Labs
...Verilog A, C, and TCL Knowledge of industry-standard interfaces. Tools proficiency in Xcelium, Spectre, Questasim, Symphony Scripting skills in languages...
23 h 9 minutes ago in Talent.comReport -
Senior/Staff Engineer, Technical Manager (Design...
MediaTek Singapore, Singapore
...coverage driven verification methodology o Implement functional and functional/code coverage closure o Hands-on code/debug with UVM, SystemVerilog, Verilog...
3 days ago in Talent.comReport -
IC Design Engineer (Verilog, EDA, up to $10,000)
Recruit Expert Singapore, Singapore
...Verilog HDL and VHDL RTL design, Logic Synthesis, DFT, ATPG, Timing ClosureSalary: $6,000 to $10,000If you are keen to apply for the position, kindly email...
2 days ago in WhatjobsReport -
Information Security Engineer
Confidential Singapore, Singapore
...programming languages such as VHDL, Verilog, C / C+ / Java / Python Passion for hardware and embedded systems development Curious mindset Show more Show less
2 days ago in FounditReport -
(Sr. /Staff) SoC Design Engineer
new OMNIVISION
...to meet or exceed the technical requirements of the SoC. You would be responsible for the successful implementation of the designs in Verilog/SystemVerilog...
1 day ago in Talent.comReport -
NVEG – NAND Silicon Design Validation (SDV) Product...
Micron Singapore, Singapore
...Verilog simulation, bench testing to probe and analyze waveforms (pairing with usage of oscilloscope, parametric analyzer), creation/optimization of NAND...
2 days ago in Talent.comReport -
Research Associate/Engineer II (FPGA Design and...
Nanyang Technological University Singapore, Singapore
...Verilog or VHDL Strong understanding of digital design principles and embedded systems Proficiency in low-level programming languages such as C, Rust and...
3 days ago in Talent.comReport -
Senior Silicon Design Engineer (FPGA)
new Advanced Micro Devices
...Verilog Strong debug skills Scripting experience using Perl, Python, TCL, C-shell, Make and/or other scripting languages Knowledge and experience with basic...
1 day ago in Talent.comReport -
Design Engineer
new BLACK SESAME TECHNOLOGIES (SINGAPORE) PTE. D1, Singapore, Singapore
Responsibilities: Assist in designing micro-architecture for ISP and CV algorithms. Perform RTL design using Verilog/System Verilog and HLS tools (Catapult)...
20 h 18 minutes ago in WhatjobsReport -
(Sr. /Staff) ISP RTL Design Engineer
Confidential Singapore, Singapore
Description Responsibilities: Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis) Define...
2 days ago in FounditReport -
(Sr. /Staff) ISP RTL Design Engineer
new OMNIVISION
Description Responsibilities: Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis) Define...
15 h 23 minutes ago in Talent.comReport
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