Verilog engineer job offers
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Snr /MTS Silicon Design Engineer
xilinx asia pacific Singapore, Singapore
...Verilog, C, and C+ Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a...
2 days ago in WhatjobsReport -
Silicon Design Engineer
Advanced Micro Devices
...Verilog, C, and C+ Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a...
3 days ago in Talent.comReport -
Front end design verification Engineer
Confidential Singapore, Singapore
Job Description Experience: 6+ years. Develop and implement constrained-random verification environments using System Verilog and UVM. Write and execute test...
30+ days ago in MonsterReport -
Digital Frontend Design Engineer๏ผSG๏ผ
Canaan Singapore, Singapore
...ownership of the full project lifecycle, from architecture to production. 5+ years of experience in ASIC frontend design. Strong proficiency in Verilog/VHDL...
2 days ago in WhatjobsReport -
Digital Implementation Engineer (Chip Design)
FOCALTRANS PTE. Singapore, Singapore
...timing ECO and analysis tasks. Job Requirements: Bachelorโs degree or above, with at least 5 years of relevant working experience. Proficient in Verilog...
2 days ago in WhatjobsReport -
Senior IC Design Verification Engineer
BITDEER DEVELOPMENT PTE. Singapore, Singapore
...datacenters in the United States, Norway, and Bhutan. What you will be responsible for Apply UVM (Universal Verification Methodology), SystemVerilog, Verilog...
2 days ago in WhatjobsReport -
Staff Silicon Design Engineer - RTL Integration
AMD Singapore, Singapore
Staff Silicon Design Engineer. RTL Integration Join AMD as a Staff Silicon Design Engineer โ RTL Integration. Work on AMDโs nextโgeneration FPGA and...
2 days ago in WhatjobsReport -
Staff Physical Design Engineer
Advanced Micro Devices
...PERSON: Strong communication skills, ability to multi-task across projects, and work with geographically spread-out teams KEY RESPONSIBILITIES: This Engineer...
3 days ago in Talent.comReport -
Senior RTL Design Engineer
Confidential D18, Singapore, Singapore
...design. Experience with logic simulators for both RTL and gate-level simulation, design/waveform browsers, and power analysis tools, Verilog RTL design
30+ days ago in FounditReport -
Semiconductor Design Verification Engineer (SOC/IP)
Realtek Singapore, Singapore
...Verilog/ UVM experience. Familiar with ASIC verification methodology, tools, and development flow. Working experience or familiar with Ethernet L2/L3...
2 days ago in WhatjobsReport -
Rtl design engineer (asic/soc)
new HKM HR MANAGEMENT PTE. Singapore, Singapore
...Verilog and SystemVerilog. Proficient in VCS, Verdi, or similar industryโstandard tools. Skilled in preโlayout and postโlayout simulation. Knowledgeable...
1 day ago in WhatjobsReport -
Senior Principal SOC Design Engineer
MAXLINEAR ASIA SINGAPORE PRIVATE Singapore, Singapore
...and drive issues to closure Job Requirements Bachelor Degree or Master's in Electronics Engineering with 12+ years of experience Expert in VHDL and Verilog...
2 days ago in WhatjobsReport -
Network Analysis Engineer
new SEARCH STAFFING SERVICES PTE. ้ขๅณถๅ, ้ขๅณถๅ
...Verilog and Python; experienced with EDA tools for protocol simulation and validation. Strong technical reading and writing skills in Chinese. No experience...
1 day ago in WhatjobsReport -
Senior Quality Engineer
Advanced Micro Devices
...C/C+/Verilog/VHDL/ Tcl/Perl/Python/Unix shells Working knowledge of Linux environment Possesses a good understanding of root cause analysis techniques...
3 days ago in Talent.comReport -
ASIC RTL Design Engineer
Confidential Singapore, Singapore
...Verilog Experience with VCS, Verdi or other industry standard tools Experience with pre-layout simulation and post-layout simulation Understanding of the...
15 days ago in FounditReport -
Principal Analog Mixed-Signal Design Engineer
new Astera Labs Singapore, Singapore
Principal Analog Mixed-Signal Design Engineer Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and...
1 day ago in WhatjobsReport -
Staff Silicon Design Engineer - RTL Integration
Advanced Micro Devices Singapore, Singapore
...Verilog/SystemVerilog HDLFamiliarity with CAD tools such as VCS, Verdi, Design Compiler, Primetime, Spyglass, Lint, Conformal, CDC/RDC tools, etc...
2 days ago in WhatjobsReport -
Senior Principal SOC Design Engineer
new MaxLinear Singapore, Singapore
...updates and improvements Qualifications Bachelor Degree or Master's in Electronics Engineering with 15 years and above of experience Expert in VHDL and Verilog...
1 day ago in WhatjobsReport -
Senior IC Mid-End Engineer (STA)
new Bitdeer Technologies Group Singapore, Singapore
...accelerators, NPUs, or custom compute engines. Proficiency in Verilog/SystemVerilog, RTL-to-GDSII flow, and EDA tools (Synopsys Design Compiler, Cadence Genus,
1 day ago in WhatjobsReport -
Senior Staff/ Design Verification Engineer
Silicon Labs
...Verilog A, C, and TCL Knowledge of industry-standard interfaces. Tools proficiency in Xcelium, Spectre, Questasim, Symphony Scripting skills in languages...
3 days ago in Talent.comReport -
IC R&D Engineer
Confidential D27, Singapore, Singapore
...circuit design from architecture to transistor level, post extraction verification and design modifications to meet requirements Digital logic design, verilog...
19 days ago in MonsterReport -
Senior Silicon Design Engineer (FPGA)
new AMD Singapore, Singapore
...Verilog Strong debug skills Scripting experience using Perl, Python, TCL, C-shell, Make and/or other scripting languages Knowledge and experience with basic...
1 day ago in WhatjobsReport -
Senior Silicon Design Engineer (FPGA)
Advanced Micro Devices Singapore, Singapore
...Verilog Strong debug skills Scripting experience using Perl, Python, TCL, C-shell, Make and/or other scripting languages Knowledge and experience with basic...
4 days ago in WhatjobsReport -
Senior IC Mid-End Engineer (STA)
BITDEER DEVELOPMENT PTE. Singapore, Singapore
...Verilog/SystemVerilog, RTL-to-GDSII flow, and EDA tools (Synopsys Design Compiler, Cadence Genus, PrimeTime, Innovus). Strong understanding of timing...
2 days ago in WhatjobsReport -
Staff/Snr Staff Physical Design Engineer
ADVANCED MICRO DEVICES (SINGAPORE) Singapore, Singapore
...(Verilog experience preferred) for high speed Datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock...
2 days ago in WhatjobsReport
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