Verilog engineer job offers
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- Within the last 7 days 59
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(Sr. /Staff) SoC Design Engineer
OMNIVISION Singapore, Singapore
...to meet or exceed the technical requirements of the SoC. You would be responsible for the successful implementation of the designs in Verilog/SystemVerilog...
2 days ago in WhatjobsReport -
Sr/ IC Design Engineer (Design Verification)
ETHOS TECH ONE PTE. Singapore, Singapore
...communication and Analytical skillsUnderstanding of HDL (Verilog, VHDL) Experience in using leading EDA software tools like Cadence/ Synopsys #J-18808-Ljbffr
2 days ago in WhatjobsReport -
Standard Cell Library Design Engineer
This is an IT support group D23, Singapore, Singapore
...verilog, lef. Lib and other industry standard EDA modelsFamiliarity with EDA tools used in STA and PnRExperience with. Lib syntax including NLDM/CCS/LVF is...
2 days ago in WhatjobsReport -
Staff/Senior Staff Engineer - Chip Verification
Singapore, Singapore
...Verilog and UVM Test Bench bring-up. Exposure to version-controlling (e.g. Git/Bitbucket, ClearCase, CVS, SVN) and bug-management schemes. Self-motivated...
6 days ago in JobleadsReport -
Senior / Staff Digital Design Engineer
new Advanced Micro Devices (S) Singapore, Singapore
THE ROLE: AMD is seeking a talented, motivated and self-driven digital design engineer to be part of the SerDes Technology group. You will be part of the...
1 day ago in WhatjobsReport -
Design Verification Engineer (SOC/IP)
Confidential Singapore, Singapore
...Verilog/ UVM experience. Familiar with ASIC verification methodology, tools, and development flow. Working experience or familiar with Ethernet L2/L3...
7 days ago in FounditReport -
Senior Design Verification Engineer (SOC/IP)
Singapore, Singapore
...Verilog, UVM, Python(TCL/Perl a plus) Familiar with ASIC verification methodology, tools, and development flow. Preferred Working experience: Ethernet L2/L3...
6 days ago in JobleadsReport -
Standard Cell Library Design Engineer
Broadcom D23, Singapore, Singapore
...circuit design knowledgeUnderstanding of cell layout or physical designUnderstanding of FinFet, RibbonFet/GAA process nodesUnderstanding of verilog...
2 days ago in WhatjobsReport -
Standard Cell Library Design Engineer
Broadcom Singapore, Singapore
...their requirements Key Requirements Digital or mixed-signal circuit design knowledge Understanding of cell layout or physical design Understanding of verilog...
4 days ago in Talent.comReport -
Senior/Staff Engineer (Design Verification)
new MediaTek D8, Singapore, Singapore
...based coverage driven verification methodology. Implement functional and functional/code coverage closure. Hands-on code/debug with UVM, SystemVerilog, Verilog...
18 h 49 minutes ago in GrabjobsReport -
Senior analog mixed-signal design engineer
Tbwa Chiat/Day D8, Singapore, Singapore
Senior Analog Mixed-Signal Design Engineer Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and...
3 days ago in jobs.searchReport -
Senior / Staff Digital Design Engineer
Advanced Micro Devices Singapore, Singapore
...Verilog/VHDL language, verification, logic synthesis, and DFT in high performance design. Experience in test planning/creation/analysis of post silicon...
3 days ago in WhatjobsReport -
Senior Staff / Principal Electrical Engineer
Illumina Singapore, Singapore
...Verilog Experience using Xilinx Vivado Design Suite Proven leadership experience in guiding engineering teams. Be curious and analytical, with a proven...
4 days ago in Talent.comReport -
Senior Field Applications Engineer
Avnet Southeast
...VHDL/Verilog/C+ programming. Experience working on AI solutions development using Caffe, Tensorflow, Keras, Pytorch frameworks is a strong plus. Experience...
2 days ago in WhatjobsReport -
Principal Analog Mixed-Signal Design Engineer
Tbwa Chiat/Day D19, Singapore, Singapore
...Verilog RTL or DSP design concepts. Knowledge of optical transceivers. Expertise in ESD protection techniques and IC packaging methodologies. We know that...
3 days ago in WhatjobsReport -
Senior/Staff Engineer, Technical Manager (Design...
MediaTek Singapore, Singapore
...coverage driven verification methodology o Implement functional and functional/code coverage closure o Hands-on code/debug with UVM, SystemVerilog, Verilog...
4 days ago in Talent.comReport -
Lead Engineer - RTL Design (Senior Staff Engineer level)
Singapore, Singapore
...ultra low-power microprocessors. The Singapore office houses the Product Development (PD) team which will be working on projects. Lead RTL Design Engineer...
4 days ago in JobleadsReport -
Senior Engineer, NVE PE - NAND Validation and...
Micron Singapore, Singapore
...(Verilog, Synopsis VCS) is a plus Effective communication skills in written and spoken English Good multitasking and organizational skills Strong...
4 days ago in Talent.comReport -
Senior Engineer / - NVE PE (Media Health - Probe)
Micron Singapore, Singapore
...to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. JR54794 Senior Engineer...
4 days ago in Talent.comReport -
[2025 Internship] Timing Signoff Engineer (CAI2/3)
new MediaTek Singapore, Singapore
...Verilog language. With knowledge in Processor verification, FPGA verification and/or Formal verification. Familiar with Synopsys ICC (preferred) or Cadence...
1 day ago in Talent.comReport -
Engineer, HIG-HBM Product Engineering (Media Health...
Micron Technology Singapore, Singapore
...Verilog simulations is crucial for the development of new products and technologies. Yield Improvement and Cost Reduction: Improving manufacturing test...
2 days ago in WhatjobsReport -
Backend Engineer – DFT/Synthesis/STA (Senior/ Junior)
Singapore, Singapore
...to achieve their goals. Join our team and be a part of our exciting journey! Apply now to become our next Backend Engineer – DFT/Synthesis/STA! J-18808-Ljbffr
7 days ago in JobleadsReport -
HIG HBM PE Principal Component Validation Engineer
Micron Technology Singapore, Singapore
...and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. As an HBM PE Principal Component Validation Engineer...
3 days ago in WhatjobsReport -
NVEG – NAND Silicon Design Validation (SDV) Senior/Engineer...
Micron Singapore, Singapore
...Verilog simulations Identify design marginalities and recommend design fix for circuit-related problems Perform electrical failure analysis to understand...
4 days ago in Talent.comReport -
NVEG – NAND Silicon Design Validation (SDV...
Micron Singapore, Singapore
...Verilog simulations Identify design marginalities and recommend design fix for circuit-related problems Perform electrical failure analysis to understand...
4 days ago in Talent.comReport
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